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Basic SR latch trigger

Last Update Time: 2018-08-28 17:26:28
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trigger

Timing logic circuits usually have feedback or memory and storage units, and the output signal is related not only to the input signal at the time, but also to the previous output state. In order to distinguish the difference between the same terminal signal before and after the change, it is usually used to distinguish the upper corner of the mark. The upper corner of the original value of standard n, n + 1 represents the new value after the change, such as Q, which represents the initial state of Q, called the current state; Q represents the new state of Q, called the sub-state. Flip-flop is the basic unit of sequential logic circuit. Flip-flop itself has a very wide range of applications. Flip flops usually have feedback inside, which can play a role in storage and memory.

Basic SR latch

SR latches are sometimes referred to as RS triggers. The SR latch is divided into a basic SR latch and a gated SR latch. The basic SR latch is the basic unit of all kinds of latches and flip-flops, and it is often used in the back-off circuit of buttons or switches. Gated SR latches are seldom used alone and usually appear in the internal structure of integrated flip-flops. The basic SR latch consists of two circuit structures, a non-door SR latch and a non-door SR latch. They all have feedback to realize the function of memory through feedback self maintenance function.

Use of state transition diagrams and annotations

(1) State transition diagram is a common tool in sequential logic circuits. It writes states in circles, arrows indicate the direction of state transition, and transition conditions are written next to arrows.

(2) Note that if there are special reasons, it will cause the SR latch to be valid simultaneously (for constraints), the output to be deterministic and Q = Q; however, when the separation is valid, DELA is valid if both input signals are invalid at the same time.

The Y time of the gate circuit is different, and the output can be state, or zero state, as shown in the shadow. For the actual SR latch connected, the output is either a defined zero state or a defined one state, because the delay duration of two integrated circuits is determined, that is, the output of the actual SR latch is determined, but actual testing is required. Therefore, when replacing integrated circuits or producing multiple products, it is impossible to guarantee the output state of integrated circuits. When the products are actually produced, the consistency of all products must be guaranteed. When designing circuits with SR latches, if not tolerated, other types of latches or flip-flops need to be selected.